5 Replies Latest reply on Jan 6, 2016 7:50 AM by Intel_Peter

    Register base address

    vamkri

      Hi,

      Can anyone help me in finding base address of i2c driver "intel_qrk_gip". I am using galileo gen2 target platform ?

        • 1. Re: Register base address
          Intel_Peter

          Hello vamkri,

           

          You can find that information in section 19.5 of the Intel® Quark™ SoC X1000 datasheet. Let us know if that information helps you.

           

          Peter.

          • 2. Re: Register base address
            vamkri

            Hi Peter,

             

            I have seen Offset start, offset end and registers default value. But there is no base address given. Can you let me know ...

             

             

            Thanks,

            Vamsi

            • 3. Re: Register base address
              Intel_Peter

              Let me investigate about this and I'll get back to you as soon as possible.

               

              Peter.

              • 4. Re: Register base address
                xbolshe

                Hi,

                 

                using lspci -vvv:

                 

                00:15.2 Serial bus controller [0c80]: Intel Corporation Device 0934 (rev 10)
                        Subsystem: Intel Corporation Device 0934
                        Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
                        Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
                        Latency: 0
                        Interrupt: pin C routed to IRQ 36
                        Region 0: Memory at 90107000 (32-bit, non-prefetchable) [size=4K]
                        Region 1: Memory at 90106000 (32-bit, non-prefetchable) [size=4K]
                        Capabilities: [80] Power Management version 3
                                Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold-)
                                Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
                        Capabilities: [a0] MSI: Enable+ Count=1/1 Maskable+ 64bit-
                                Address: fee0100c  Data: 4142
                                Masking: 00000000  Pending: 00000000
                        Kernel driver in use: intel_qrk_gip
                        Kernel modules: intel_qrk_gip
                
                

                 

                and using dmesg | grep qrk:

                 

                
                root@quark:~# dmesg | grep qrk
                [   12.345633] intel_qrk_gip 0000:00:15.2: enabling device (0000 -> 0002)
                [   12.426587] platform qrk-gpio-restrict-sc.0: Driver qrk-gpio-restrict-sc requests probe deferral
                [   12.532884] intel_qrk_gpio_probe UIO addr 0x90106000 internal_addr 0xd06ee000 size 4096 memtype 1
                [   12.543147] intel_qrk_gip 0000:00:15.2: i2c speed set to 100kHz
                [   12.703588] intel_qrk_gip 0000:00:15.2: enabling bus mastering
                [   12.704264] platform qrk-gpio-restrict-sc.0: Driver qrk-gpio-restrict-sc requests probe deferral
                [   13.052516] platform qrk-gpio-restrict-sc.0: Driver qrk-gpio-restrict-sc requests probe deferral
                
                

                 

                it is possible to identify I2C BAR = 0x90107000

                 

                BR,

                xbolshe

                • 5. Re: Register base address
                  Intel_Peter

                  Hello vamkri,

                   

                  The Galileo's I2C MM registers are located at the base address defined by BAR0 (Base Address Register 0) of PCI device 21, function 2. It can be found in table 105 of the X1000 Datasheet for Processors.

                   

                  Peter.