http://h21007.www2.hp.com/portal/StaticDownload?attachment_ciid=6ea864c3c39f111064c3c39f1110275d6e10RCRD&ciid=6308e2f5bd… - page 34. Considering our discussion in What about 64-bit IA-32 and Itanium? , pages 17-20 counts EPIC architecture issues and page 22 shows, how Intel tried to solve them - well, just throw more execution units!
Thank you for your reply, the document your provided is excellent. In page 34, it says,
Itanium Itanium 2 Bus Type Split Address/Data Split Address/Data Data Bus Size 64 bits of data + ECC = 72 bits 128 bits of data + ECC = 144 bits Double-pumped data bus? Yes, 266 MT/sec Yes, 400 MT/sec Data Bus Line Size 64 bytes 128 bytes Data Bus Bandwidth 2.1 GB/sec @ 133 MHz 6.4 GB/sec @ 200 MHz Bus Ratios supported 2:n where 8<=n<=16 2:n where 8<=n<=23 Bus Frequency 133 MHz (with 4 CPUs) 200 MHz (with 4 CPUs) Processors Supported/bus up to 4 up to 4
I represent it as the above table, where one should care that the FSB of Pentium 4 is Quad-pumped, where both Itanium and Itanium 2 is double-pumped. The data bus line(cache line) size of Pentium III is 32 bytes, Pentium 4 64 bytes, Itanium 64 bytes and Itanium 128 bytes.