Thanks for reply! But what does "lanes are handled by the BMC directly" mean?
You mean that the PCIe Gen2 x4 lanes are first connect to the BMC, then the BMC route these lanes to the mezzanine module slot?
Like this? That is really weird!
Even though, it doesn't answer my question. Let's assuming the PCIe Gen2 x4 lanes are first connect to the BMC,
i3 has only 16 PCIe lanes and they are already used by Slot 4, Slot 5 and Slot 6.
So where does the extra PCIe Gen2 x4 lanes come from?