5 Replies Latest reply on Nov 7, 2015 7:21 AM by dmccoy

    Using Intel Edison to Interface with FPGA through SDIO

    dmccoy

      Hello,

       

      I want to interface Intel Edison with my FPGA using a high throughput interface such as SDIO found on the 70 pin breakout connector. I was looking through the 'Intel Edison Compute Module Hardware Guide' Document Number: 331189-004 on page 22 section 'SD Card Interface' under the fourth bullet point it states that 'Only supports SD memory.' Is this a software or hardware limitation?

       

      Dave

        • 1. Re: Using Intel Edison to Interface with FPGA through SDIO
          DiegoV_Intel

          Hello dmccoy,

           

          The SD 3.0 interface by design is hardware built at the silicon level of the SoC. It isn't a limitation; it has been designed for SD cards. If you want to use it for any other device like FPGA you need to build an interface for the FPGA that follows the SD 3.0 specification as described in Home - SD Association.

           

          Regards,

          Diego.

          • 2. Re: Using Intel Edison to Interface with FPGA through SDIO
            dmccoy

            Diego,

             

            Thank you for getting back to me! Regarding your answer, I thought as much. I'm designing and building a board that should take advantage of the SDIO bus, here is a couple of renderings of it:

             

            (Intel Edison is the white box on the lower right)

             

            Nyx Top.png

            Nyx Isometric.png

             

            I'm working on the SDIO core right now. It will be challenging (but fun) to debug.

             

            Thanks again,

             

            Dave

            • 3. Re: Using Intel Edison to Interface with FPGA through SDIO
              dmccoy

              Passed the smoke test, both the FPGA and the Edison are working fine

               

               

              Nyx Rev A.jpg

               

              Still a lot to do but things are promising

              • 4. Re: Using Intel Edison to Interface with FPGA through SDIO
                KurtBreish

                dmccoy, so how did your work with using the SD interface to interface with an FPGA come out?

                I imagine that you had problems turning off caching.  Were you able to accomplish that?

                I would like to do the same thing, and was wondering if you had any words of advice.

                Kurt

                • 5. Re: Using Intel Edison to Interface with FPGA through SDIO
                  dmccoy

                  Kurt,

                   

                  It's still ongoing. I spent the last couple of months (when I had a fee moment) writing an SDIO device in HDL:

                  CospanDesign/sdio-device at DDR · GitHub

                  In order to exercise it I wrote an SD Host:

                  nysa-verilog/verilog/wishbone/slave/wb_sd_host at master · CospanDesign/nysa-verilog · GitHub

                   

                  This took quite a while to get right but I've tested it out on a single FPGA with both the SD host and SDIO device in a funny loopback configuration. I made some mistakes but in the end It was able to communicate and send data back and forth using DDR.

                   

                  I figured out how to get my SDIO driver built and downloaded to the Edison. I decided that, at first, I'll just build a character driver that is similar to spidev. Currently the driver just loads and I haven't had to face this caching issue. When I do... I don't know... a new challenge

                   

                  After I found that I could load the driver I have been focusing on loading the FPGA image from the Edison into the SPI flash chip, this way I should be able to exercise the driver and the SDIO device core. I, initially, thought that I would need to write a low level spidev SPI flahs writer in c but then I found MRAA and thought all my problems were solved. Unfortunately I am having a hard time with the Python bindings of the MRAA SPI controller and this Winbond SPI Flash chip. The documentation for MRAA says I need to configure the driver to control the chip select automatically but when I probe the chip select line with my scope I see that it doesn't go low at all. I thought that perhaps I didn't declare the bus correctly but because I see SPI clock, SPI MISO and SPI MOSI working then obviously it is the correct but I can't configure the chip select. I played around with manually controlling the chip select and that works..ish. I can recognize the SPI flash chip, erase it, and get part way through the writing process... then it barfs and I don't know why... it seems as through the driver crash... which reminds me I should check dmesg... just checked nothing, the driver just freezes.


                  I am delving into MRAA's source to search for what I am missing and look for what's wrong with the chip select.


                  Dave