I am guessing there is a question in here someplace?
Looks like you did not flash the code sack onto the unit, specifically the SDRs
Range for Sandy Bridge CPUs (V1) and Ivy Bridge CPU V2 are different.
Lower non-critical (6Ah = 0.59 Volt) for Ivy Bridge
Lower non-critical (73h = 0.64 Volt) For Sandy Bridge
The correct values are loaded automatically when you flash the FRUSDRs.
Also, ipmi-sel is not the best tool for reading the SEL.
The SELVIEW tool on the support page will provide more info, like if the event is being ASSERTED or DE-ASSERTED
Every other one you are showing is a DE-ASSERT when the core voltage returns to normal range.
Oh, one more answer sinf no question was asked, the core voltage will vary as the processor moves from Power saving speed step to Turbo boost mode.