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For the Core 2 Architecture ther had been the bits 9 and 19 on msr 0x1a0 which could be set to disable the hardware and the adjacent cache line prefetcher. This feature is described in the "Software Developer’s Manual Volume 3B: System Programming Guide, Part 2" pp B46-B47.
For Nehalem/Core i7 this functionality is not documented. Is this information confidential and only part of a "BIOS Developer Guide"?