It's been a while; but I have been debugging the design as time permits. Upon initial assembly using a hot skillet reflow in the garage; I had some issues with the Edison high-density connectors. After getting that sorted; the USB hub and PATA chip identified themselves to my netbook. putting a USB memory stick on the DD interface of the hub showed that I could read/write the USB bus.
The USB hub is seen by the Edison in "host mode" and by J16 (host computer) in device mode. I can download Arduino sketches via J16 when in device mode.
Initial debug showed several issues:
- the PL2571B USB->SATA chip wasn't being seen on the USB hub. Later tracked down to a bad solder joint on the clock generator's RE17 22ohm series resistor. After fixing that; the SATA interface shows up as USB Mass Storage. I do not currently have my SSD available at home work bench; so will retrieve it from the initial test bed tomorrow.
- the Cypress AT2LP (USB->PATA) chip is being seen on the usb bus; but because I didn't wire in an EEPROM - It won't allow me to install drivers for it.
- U36 was the wrong package; so I can't power J16 when in host mode.
- The U5/UE6/UE7 eeprom connections don't work because there doesn't appear to be enough bandwidth in UE6 - a risk I took in the initial design; but in retrospect was flawed to begin with.
- J3 - the FTDI USB debug interface to the Edison kernel had some solderablity issues around J3 - I think due to close proximity to un-tented vias near the pins of J3. Was able to workaround the issue using some detail soldering - but will need to be fixed in the final design with tenting of vias - and possibly moving some of them.
I'm going to try and find the right package for U36 and more importantly figure out how to dead-bug rework a EEPROM to the AT2LP to see if I can get that interface online in the near future.
The other thing which needs to be done; but is likely beyond my home workbench capabilities is to do a USB dataeye analysis to see if there is any margin in the design.
After attaching a I2C eeprom to the AT2LP; the PATA interface came up.
mSATA interface is working fine.
Basically; all of the interfaces are working as expected including the USB muxes in the design.
Been working on FabB of the design; correcting minor issues found. Really all I need to do is add a I2C eeprom to the PATA controller and correct the I2C eeprom on SATA. No sense of urgency here as there seems to be little interest in this design publically.