I just tested this with the breakout by sending a test string through /dev/ttyMFD1. On the first picture the port was set at 9600, then we switched it to 115200 (see second image). As you can see the image is not as clear as the first one. In last picture we increased the sampling rate of the logic analyzer and we got a clearer signal. Have you tried increasing the number of samples per second of the device you are using to read the port?
- /dev/ttyMFD1 at 9600. Logic Analyzer at 5MHz on the Digital Channel, 625kHz on Analog Channel.
- /dev/ttyMFD1 at 115200. Logic Analyzer at 5MHz on the Digital Channel, 625kHz on Analog Channel.
- /dev/ttyMFD1 at 115200. Logic Analyzer at 100MHz on the Digital Channel, 5 MHz on Analog Channel.
We just tested the serial port at 1MBd sending packets of 64 bytes. There were no intercharacter gaps in that case and bit time 1us. That makes sense as the FIFO is 64 bytes long, so once transmission starts it should all be handled by the UART. We will be taking a measurement with transmitting a longer packet tomorrow probably.
I can take some DSO snapsshots if you like.