3 Replies Latest reply on Dec 31, 2014 2:45 PM by JPMontero_Intel

    Edison DC in jack problem

    BryanB

      I've been using my Edison successfully for a bout a week simply using USB-provided power.  I decided to switch to using an external DC supply via the DC in barrel connector.

       

      Noting the spec allowed for up to either a 15V or 17V input (depending on which document you look at; the step down converter IC allows an input up to 17VDC according to the TI datasheet) I connected a 15VDC supply to the input and then

       

      POP!

       

      That terrible sound followed by that terrible smell.

       

      Thinking my supply had become defective I measured its open circuit voltage at 15VDC, as expected.

       

      Fearing the worst, I was pleased however when the Edison powered up normally when I switched back to USB power.  No widespread damage.


      I switched back to the DC in jack this time using a bench supply where I could limit the current.  The supply indicated a nearly dead short reaching the programmed current limit immediately.  The board wouldn't boot (obviously).

       

      I was ready just to assume I had a defective board, but decided to look at the schematics anyway.  I found this in the DC input section:

       

      snapshot6.png

       

      I looked up the datasheet for U1 and found that C4 on pin 9 (SS/TR) is related to the startup of the switcher which means it is probably internally exposed to VIN (up to 17V) rather than VOUT (5V).  The 6.3V rating on C4 immediately looked suspicious (too low).  Checking the datasheet confirms that the cap on SS/TR must be a 25V device.  If I applied 15V to that 6V cap, it would almost certainly pop.

       

      snapshot7.png

       

      Question for Edison folks at Intel: Does this schematic diagram reflect the manufacturing values?  If so, have you applied 15V or 17V to the DC in jack?  What happens?  Did I just get a bad board or is this a design problem?

       

      Thanks for you help, and I love the capabilities that this board provides!

        • 1. Re: Edison DC in jack problem
          Tage

          the Intel engineers should know more about this, but I see a couple of potential issues with the dc jack input regulator U1. the softstart capacitor voltage rating is not in the list, because I think that the voltage across it does not exceed 2V. the charge current into the cap is also very weak so even if the cap was shorted it would just prohibit the circuit from starting. the pop must have come from some other component or perhaps a circuit board trace.

           

          my own list of concerns and thoughts:

          1. my main concern is that the inductor L1 is a very tiny component and has a saturation current of around 1A. it is physically too small. if the current exceeds saturation, the inductance will drop. the datasheet mentions that the steady state current limit can be as high as 4.9A, and that during transient conditions the current can be much higher, due to the inherent delays. it takes some time to shut of the current when overcurrent is detected. during that time, the current will continue to rise at a rate that is determined by the inductance. now, if the inductor has saturated the inductance value can be only a small fraction of the nominal value, so it is possible that the maximum current could be a lot higher than 4.9A. this puts a very high stress on the IC.

          I have not done any testing on my own boards to see if such overcurrent actually occurs.

           

          2. there is a diode CR2 between the output capacitor C1 and the point where output voltage is measured. if the output voltage overshoots at startup, this could cause a situation where the controller tries to correct by sucking current from the output cap. this current is thrown back into the input side capacitor. it may be that this reverse current is quite high, adding a stress to the controller that does not occur during normal operation. whenthe 5V comes up, the loads may not immediately start drawing current, so it may be possible that the 5V overshoots, creating this situation because of CR2. one question is if the reverse current from C1 could cause the input capacitor voltage to briefly rise higher than the external power supply voltage.

           

          3.the max voltage rating for the controller is 20V, so it is important that the input voltage does not exceed this value even briefly. but there is only small ceramic capacitors on the input side, no overvoltage protection and no electrolytic capacitor that could dampen the voltage oscillation that occurs when a power supply is plugged in. if the wires to the power supply are long, the wire inductance will form an LC circuit with the ceramic capacitor C47 and it is possible that the input voltage rings to twice the power supply voltage. this could be a problem.

          • 2. Re: Edison DC in jack problem
            BryanB

            I had noticed that L1 was also out of spec, but assumed that was OK because the steady state current through the inductor wouldn't exceed 1 A which is well below the 3 A steady state capability of the buck converter.  I could find nothing in the literature that allowed for that reduction in L, however.

             

            I think you are probably correct about the 6.3 V cap not being the problem as I measured the resistance across it and there was no short.  I cannot find what is shorted, however.

             

            Your points about what might be happening when power is first applied are interesting.  I mocked up a similar DC-DC converter and used a scope on the input side to view what happens when I apply power via the 15V DC supply I used that fried the Edison DC-in stage.  The voltage at the DC-in jack in my mock up initially overshoots beyond 17 V, the safe limit for the Edison buck converter in question, but I didn't make note of what the actual voltage was or whether it passed the absolute max limit.  As a second experiment, I unplugged the 15 V supply from the 120VAC supply, plugged the DC output into my mockup and then plugged the supply into 120VAC and there was no such glitch (the overshoot is a few hundred mV at most).  This is probably the right way to apply power to the Edison given how the DC-in stage is designed.

             

            It's possible that people using a 12 VDC supply on the barrel connector (probably the most common situation) are getting away with hot plugging because of the 3 extra volts of margin compared to my situation.  Or my 15 V supply is unusually prone to overshoot when suddenly presented with a load.  Of course I only got one chance for this to fail :-) so maybe I did indeed just have a marginal board.  Intel told me to send it back from replacement.

             

            I am also curious about the placement of the voltage sense line on the other side of the Schottky diode.  This is a nice idea in that it should allow the 5V rail to truly run at 5V instead of ~4.5V that would result after the forward voltage drop of the diode, but the diode introduces a non-linearity in the feedback loop of the buck converter.  While I couldn't find any spec on the diode indicated in the schematics, if it's forward voltage drop is around 0.45 V (which is consistent with measurements of the "5V" rail being at 4.5 V) then the buck converter sees 0 V of feedback until the output voltage of the converter rises above 0.45 V and the diode conducts.  What does it do during that window of seeing no feedback?  I couldn't find any application notes that showed that family of buck converter used with a diode in the feedback loop.

             

            I am a VLSI guy so I admit to being out of my professional depth on the topic of switch mode power supply design.  It's just my intent to ask questions and try to understand what went wrong so I don't have a repeat of this situation when I get the replacement board.  I know engineers don't like being second guessed, and there may be nothing at all wrong with the design.  :-)

            • 3. Re: Edison DC in jack problem
              JPMontero_Intel

              Hi BryanB,

               

              Thank you for your feedback. We are currently looking into it.

               

              Regards,
              JPMontero_Intel