9 Replies Latest reply on Aug 1, 2016 4:14 AM by The-Count

    Edison CPU specifics

    GlenEnglish

      Hi

      I am looking for the CPU specific documentation for the Z34 Atom in the Edison.

       

      Like, how much cache does it have and what,

       

      instruction set support, execution pipeline etc details, 

       

      extensions  like SSE, vector math  etc

       

      Cannot find it anywhere.... IE the hardcore person's datasheet...

       

      does anyone have any ideas? If it is available, Intel have hidden it well......

      Intel: searching "Z34 datasheet" or :"Edison datasheet" SHOULD bring up results.

       

      regards

      glen

        • 1. Re: Edison CPU specifics
          Andre.M

          root@edison:/# cat /proc/cpuinfo
          processor       : 0
          vendor_id       : GenuineIntel
          cpu family      : 6
          model           : 74
          model name      : Genuine Intel(R) CPU   4000  @  500MHz
          stepping        : 8
          microcode       : 0x810
          cpu MHz         : 500.000
          cache size      : 1024 KB
          physical id     : 0
          siblings        : 2
          core id         : 0
          cpu cores       : 2
          apicid          : 0
          initial apicid  : 0
          fdiv_bug        : no
          f00f_bug        : no
          coma_bug        : no
          fpu             : yes
          fpu_exception   : yes
          cpuid level     : 11
          wp              : yes
          flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe nx rdtscp lm constant_tsc arch_perfmon pebs bts xtopology nonstop_tsc aperfmperf nonstop_tsc_s3 pni pclmulqdq dtes64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 movbe popcnt tsc_deadline_timer aes rdrand lahf_lm 3dnowprefetch ida arat epb dtherm tpr_shadow vnmi flexpriority ept vpid tsc_adjust smep erms
          bogomips        : 998.40
          clflush size    : 64
          cache_alignment : 64
          address sizes   : 36 bits physical, 48 bits virtual
          power management:

          processor       : 1
          vendor_id       : GenuineIntel
          cpu family      : 6
          model           : 74
          model name      : Genuine Intel(R) CPU   4000  @  500MHz
          stepping        : 8
          microcode       : 0x810
          cpu MHz         : 500.000
          cache size      : 1024 KB
          physical id     : 0
          siblings        : 2
          core id         : 1
          cpu cores       : 2
          apicid          : 2
          initial apicid  : 2
          fdiv_bug        : no
          f00f_bug        : no
          coma_bug        : no
          fpu             : yes
          fpu_exception   : yes
          cpuid level     : 11
          wp              : yes
          flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe nx rdtscp lm constant_tsc arch_perfmon pebs bts xtopology nonstop_tsc aperfmperf nonstop_tsc_s3 pni pclmulqdq dtes64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 movbe popcnt tsc_deadline_timer aes rdrand lahf_lm 3dnowprefetch ida arat epb dtherm tpr_shadow vnmi flexpriority ept vpid tsc_adjust smep erms
          bogomips        : 998.40
          clflush size    : 64
          cache_alignment : 64
          address sizes   : 36 bits physical, 48 bits virtual
          power management:

          • 2. Re: Edison CPU specifics
            GlenEnglish

            Hi Andre

            Thanks for that information. Waiting for my dev boards to arrive.

             

            Right, so it is not cut down- it is pretty much the full processor minus the video crap.

             

            With thanks

            • 3. Re: Edison CPU specifics
              Andre.M

              you are welcome

              • 4. Re: Edison CPU specifics
                GlenEnglish

                I think this platform / processor is really going to catch some of the ARM users (like myself) ,and ARM vendors by surprise.

                 

                1MB cache  is a big deal compared with the 128k L2 on many vendor's ARM offerings, even with the ARM fast context switch if used...

                 

                I am a  cortex A5 fan (Atmel SAMA5D3 on 65 nm process) , nice low power, 64 bit internal dataparh, but this ATOM dual really eats the A5 for breakfast.

                 

                There is no contest....

                I suspect the Intel 22nm advantage is going to pay dividends for them.

                 

                regards

                • 5. Re: Edison CPU specifics
                  mmi

                  GlenEnglish

                  I agree and don't forget the additionally builtin MCU which will be hopefully activated with the next os release.

                  • 6. Re: Edison CPU specifics
                    GlenEnglish

                    Right now we have no data or info on the datapath/bandwidth  between the MCU and the main device, I've tried to get that from Intel, but they're not telling.

                     

                    This is a pity, as experienced, serious engineers will not take something like this seriously (despite how good it is) unless they can get the data sheets and comprehensive user manuals.

                     

                    Intel are you listening ? it's not just hobbyists out here.....

                     

                    Glen.

                    • 7. Re: Edison CPU specifics
                      deium

                      As for SSE and extensions, I would use /proc/cpuinfo to see the various flags.

                      fpu                 Onboard FPU (floating point support)

                      vme                 Virtual Mode Extensions (8086 mode)

                      de                  Debugging Extensions (CR4.DE)

                      pse                 Page Size Extensions (4MB pages)

                      tcs                 Time Stamp Counter (RDTSC)

                      msr                 Model-Specific Registers (RDMSR, WRMSR)

                      pae                 Physical Address Extensions (support for more than 4GB of RAM)

                      mce                 Machine Check Exception

                      cx8                 CMPXCHG8 instruction (64-bit compare-and-swap)

                      apic                Onboard APIC

                      sep                 SYSENTER/SYSEXIT

                      mttr                Memory Type Range Registers

                      pge                 Page Global Enable (global bit in PDEs and PTEs)

                      mca                 Machine Check Architecture

                      cmov                CMOV instructions (conditional move) (also FCMOV)

                      pat                 Page Attribute Table

                      pse36               36-bit PSEs (huge pages)

                      clflush             CLFLUSH instruction

                      dts                 Debug Store (buffer for debugging and profiling instructions)

                      acpi                ACPI via MSR (temperature monitoring and clock speed modulation)

                      mmx                 Multimedia Extensions

                      fxsr                FXSAVE/FXRSTOR, CR4.OSFXSR

                      sse                 Intel SSE vector instructions

                      sse2                SSE2

                      ss                  CPU self snoop

                      ht                  Hyper-Threading

                      tm                  Automatic clock control (Thermal Monitor)

                      pbe                 Pending Break Enable

                      nx                  Execute Disable

                      rdtscp              RDTSCP

                      lm                  Long Mode (x86-64: amd64, also known as Intel 64, i.e. 64-bit capable)

                      constant_tsc        TSC ticks at a constant rate

                      arch_perfmon        Intel Architectural PerfMon

                      pebs                Precise-Event Based Sampling

                      bts                 Branch Trace Store

                      xtopology           cpu topology enum extensions

                      nonstop_tsc         TSC does not stop in C states

                      aperfmperf          APERFMPERF

                      nonstop_tsc_s3      TSC doesn't stop in S3 state

                      pni                 SSE-3 (“Prescott New Instructions”)

                      pclmulqdq           PCLMULQDQ instruction (carry-less multiplication — accelerator for GCM)

                      dtes64              64-bit Debug Store

                      monitor             Monitor/Mwait support (Intel SSE3 supplements)

                      ds_cpl              CPL Qual. Debug Store

                      vmx                 Hardware virtualization: Intel VMX

                      est                 Enhanced SpeedStep

                      tm2                 Thermal Monitor 2

                      ssse3               Supplemental SSE-3

                      cx16                CMPXCHG16B

                      xtpr                Send Task Priority Messages

                      pdcm                Performance Capabilities

                      sse4_1              SSE-4.1

                      sse4_2              SSE-4.2

                      movbe               MOVBE instruction

                      popcnt              POPCNT instruction (Hamming weight, i.e. bit count)

                      tsc_deadline_timer      Tsc deadline timer

                      aes                 AES instructions: AES-NI

                      rdrand              The RDRAND instruction (hardware random number generator)

                      lahf_lm             Load AH from Flags (LAHF) and Store AH into Flags (SAHF) in long mode

                      3dnowprefetch       3DNow prefetch instructions

                      ida                 Intel Dynamic Acceleration

                      arat                Always Running APIC Timer

                      epb                 IA32_ENERGY_PERF_BIAS support

                      dtherm              Didn’t find a definition

                      tpr_shadow          Intel TPR Shadow

                      vnmi                Intel Virtual NMI

                      flexpriority        Intel FlexPriority

                      ept                 Intel Extended Page Table

                      vpid                Intel Virtual Processor ID

                      tsc_adjust            Didn’t find a definition

                      smep                Supervisor Mode Execution Protection

                      erms                Enhanced REP MOVSB/STOSB

                      • 8. Re: Edison CPU specifics
                        deium

                        I would imagine for those that serious, Intel probably has NDAs available.

                        • 9. Re: Edison CPU specifics
                          The-Count

                          So, can windows 10 IoT core can be installed on edison