I am using Bayleybay CRB (Baytrail Soc) with Intel FSP and coreboot. I can suspend and resume from power button successfully. However if I try to wake system from S3 using WOL (PCI Express card supporting WOL) I am unable to wake the system.
WOL works fine with BIOS and same linux image.So the difference is BIOS vs Coreboot. I took dsdt from bios, disassembled it and included in coreboot so now my linux image and dsdt are same, but wake from PCIe card still does not wake with coreboot.
I posted query on coreboot mailing list ([coreboot] WOL/PCI PME wakeup from S3 Baytrail SoC (Bayleybay CRB)) but didn't get much help. Problem seems to be GPIO configuration difference between coreboot and BIOS for GPIO_S5 and GPIO_S5.
Linux logs (posted below) matches between coreboot and bios builds when it goes to suspend. Can someone please help to figure out GPIO configuration as PCIe slot1 and slot 3 wakeup signal is connected to GPIO_S5[ and GPIO_S5[ respectively.
How does BIOS configures GPIO_S5 and GPIO_S5 pins? I do not have BIOS source so looking for help to get wake signal from PCIe slot to reach to SoC so that SoC can wake the platform.
My linux ACPI logs when going to suspend.
PM: late suspend of devices complete after 371.402 msecs pcieport 0000:00:1c.0: System wakeup enabled by ACPI r8169 0000:01:00.0: System wakeup enabled by ACPI PM: noirq suspend of devices complete after 55.586 msecs ACPI: Preparing to enter system sleep state S3 PM: Saving platform NVS memory Disabling non-boot CPUs ... smpboot: CPU 1 is now offline