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DRAM timing parameters- tccd and tburst

vvaib
Novice
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Hi,

I have been reading DRAM column read protocol which is basically defined by three timing

paremeters (1) tcas (2) tccd - column to column delay and (3) tburst- data burst duration

I am not able to understand the timing parameters (2) and (3). The text which I am reading

says that tccd is DRAM internal burst length and duration of the data burst on data bus is tburst.

Can anybody explain me these two timing parameters and why they are named so?

 

 

 

Figure 5. Shown below are pair of "back-to-back" reads. Our example Row Cycle Time (tRC) lets us transfer up to 16 bytes of data with a minimum Page open time of 24T using CL-tRCD-tRP-tRAS timings of 6-6-6-18

Thanks.

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Allan_J_Intel1
Employee
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Thanks for joining the Processor community.

Please answer the question below that way I can provide proper department of support.

Are you developing any software or hardware?

Allan.

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