0 Replies Latest reply on Nov 14, 2014 2:59 AM by SpiderKenny

    FPGA on top of Galileo

    SpiderKenny

      As part of some research I am doing, I'm devloping an FPGA board that will sit on top of Galileo.

      On it there are a number of buttons and an OLED display, to form a user interface, along with a quadrature encoder for entering values.

      There is also an Infrared receiver, and a DHT22 (AM2303) temperature and humidity sensor. One final touch is a 1-Wire Dallas iButton reader for ID.

       

      This could all be done with a none-fpga board with various interfaces to Galileo's IO headers, but then Galileo's processor would have to do all the protocol decoding, quadrature decoding, IR Receiver decoding and so on, as well as poll the keyboard buttons and update the display.

       

      On an FPGA this is all done in hardware. This does not mean that there is a soft processor in there stepping through instructions in code, but the FPGA is configured as actual logic circuits, doing real-time parallel processing of everything. It can communicate with the DHT22 and decode the keyboard, and decode an IR stream, and decode the quadrature decoder all at the same instant in time, not like a micro-processor stepping through instructions, and switching tasks, and giving the impression of real-time, but actually in real time, all in parallel, without one process taking time away from another, or without missing even the shortest of transitions on an IO line.

       

      One of the biggest challenges of using FPGAs is getting your head around the fact that the HDL (VHDL or Verilog) 'code' that you write is not procedural, but is rather the definition of hardware logic. There is a complete step-change in thinking that has to occur to understand that every line of code can get executed at the same instant, because it defines a hardware logic expression of your intention, not a step-by-step instruction on how to carry out some procedure. You can of course build step-by-step logic, using state-machines and conditional gates and so on, but you do this for each task and then every task runs at the same instance in time, they are not time-shared. It's a fascinating world and one which is well worth a look into.

       

      I will share more of the hardware and verilog code as I go along.

      To develop this I am using a Lattice MachXO2 Breakout board, and a great book on verilog is Bob Zeidman's Introduction to Verilog.

       

      Message was edited by: Kenny Millar - changed spelling of Bob Zeidman.