4 Replies Latest reply on Aug 28, 2014 8:59 AM by allan_intel

    How are L2 Cache TLB managed?




      I would like to know how L2 Cache TLB entries are managed during use. I have two specific questions.


      1) Are L2 cache TLB entries evicted when a page fault occurs from the used entry? For example, the L2 cache TLB entry has N/X bit set but the access is an instruction fetch.


      2) If the L2 cache TLB doesn't have a TLB entry for a virtual address, but the L1 cache TLB does have an entry for the virtual address, does the L1 cache TLB entry get promoted or copied to the L2 cache on access/use?


      My questions are very relevant for L2 unified caches.