Should different processor families have different behaviors for managing unified L2 cache TLB entries? Can you comment one whether different processor families have different L2 cache TLB management?
I am really only concerned with any processors with a unified L2 cache. I am led to believe that this includes all processors after 2008 which have the nehalem architecture or newer.
Thanks for your patience.
I got response from engineering team: We strongly recommend contacting our developer forum, we regret to inform that at this level, this type of information is not available through this channel.