Hello MSumulong, thank you very much for contacting us through Intel Communities.
I’m going to make some research on the information you are requesting.
Would you please provide me the model number of your system?
The system is not a desktop machine. It is a custom mainboard based on the Intel Cedar Trail platform. It has an Intel Atom N2600 CPU and an Intel NM10 Express chipset.
I just got response from engineering and according to them this chipset contains a System Management Bus (SMBus) Host interface that allows the processor to communicate with SMBus slaves.
You can confirm this information on page 41 of the cited Datasheet that can be found as a reference at the following web site: https://www-ssl.intel.com/content/dam/www/public/us/en/documents/datasheets/nm10-chipset-datasheet.pdf
Also reviewing the listed sections, the first one is related to the basic functions associated to this Bus, and the 2.14 is complementary because it is related to SMBus external conditions or other devices connected to it.
Due to these facts, there is just one SMBus that is associated to the sections listed by you on your original post.
Thanks for finding out that information. I have a followup question, in Section 2.14, I believe it refers to the SMLINK[1:0] lines and I was wondering how/what controls those lines.
I’m checking this information for you. I’ll keep you posted.
The SMlink bus is associated to the TCO functionality, so please check section 5.35, specifically on pages 91 and 92 of the cited Datasheet.
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