5 Replies Latest reply on Sep 5, 2014 12:06 PM by caseyh

    Galileo UART driver

    Lifu

      One of our customer is porting their OS onto x86 UART driver. We got a question about UART dirver which I have little exeperience on. Is there anyone who knows this area can please comment/confirm this?

       

      "We are looking into UART registers and  as per section 18.5 of the Quark data sheet, we are able to read the BAR0 contents from Yocto linux ,with Bus 0, Device:20 Function:5 offset:10h for UART1 and Bus:0 Device:20 Function:1 offset:10h UART0(ref Section 6.3)

       

      In Yocto we got BAR0 as 0x9000F000 (Physical address) with the following procedures.

      PCI configuration for UART0  (BAR0  Bus:0, Device:20 Function:1 offset:10h)

      MyCfgAddr[23:16] = 0; MyCfgAddr[15:11] = 20; MyCfgAddr[10:8] = 1;

      MyCfgAddr[7:0] = 10h; MyCfgAddr[31] = 1;

      outl(0xCF8, MyCfgAddr)

      Register_Snapshot = inl(0xCFC)  // got the address 0x9000F000

      Using mmap (map from physical to logical address) we mapped all other registers and got similar values as mentioned in the data sheet (also shown in the below thread).

       

      Similarly we are able to get the base address of UART1 as 0x9000B000 (function 5). To confirm this we have written a char into TX buffer of UART1 and it displayed in the debug console with Galileo board.

       

      So we believe that UART registers are memory mapped."