1 Reply Latest reply on Apr 9, 2014 5:39 PM by dferyance

    Open Source PCIe Soft IP Core

    mjstanis

      Hi everyone,

       

      I'm wrapping up the architecture of the Galileo shield (Developing a New Galileo Shield), which I'll post about soon, and I had a question regarding coding the RTL for the FPGA onboard.

       

      Currently, I'm looking at FPGAs and it looks like Lattice might have an FPGA that does a lot of cool stuff, but unfortunately it doesn't come with PCIe IP without paying for a license.  As I'm trying to keep everything free and available, I've been negotiating with them to see if we can come up with a free solution, similar to the Xillybus solution (www.xillybus.com) I came up with when looking at the Altera Cyclone IV with PCIe hard IP.

       

      However, I'm beginning to think it might be easier to just find an open source PCIe soft IP core out there to convert from Altera/Xilinx or get help writing one with the community (which might be quite a bit of work).  So far, I haven't been able to find much on OpenCores, Google, etc in the way of an open source PCIe soft IP core.

       

      Does anyone have any good suggestions on open source cores that we could either use or possibly convert to Lattice?  Would anybody be interested in helping write a community-based open source PCIe IP core?

       

      Thanks!

      Matt

        • 1. Re: Open Source PCIe Soft IP Core
          dferyance

          While it is a little odd to respond as I don't have an answer, I will add a few ideas. I too did some searching and it seems PCIe with FPGAs is very proprietary. This is consistent with what you found; Altera seems like the easiest way to go. Maybe instead of doing PCIe on the FPGA, use a bridge chip to another interface? I found an interesting chip here: http://www.asix.com.tw/products.php?op=pItemdetail&PItemID=119;74;110&PLine=74

          It has quite a few IO features. It doesn't really let a FPGA take advantage of the PCIe features or speed but the IO features sound similar to what you had in mind. 8 GPIO seems kind of low though. Maybe there is something else out there with a faster serial interface that wouldn't require a costly IP.

           

          What happened to the dual Lattice / Altera idea? Was it too expensive? Cost was my concern rather than the complication of integration.

           

          I wouldn't be of much use writing a PCIe core -- way beyond my skill level -- but I do know VHDL and basic digital design so I could help on much simpler things.