2 Replies Latest reply on Jan 31, 2014 1:20 AM by fmue

    PCI byte-access latency with ICH7M ?


      Hi all,


      we're experiencing timing differences on the PCI bus with ICH7M chipsets relative to an older 852GM board,  insights much appreciated:

      Boards in question are Advantech's PCI-6886 and PCI-7030 (both are PCI slot-cards), specified with having above chipsets. Operating system is Linux kernel 3.8.8 . lspci shows:
           00:1e.0 PCI bridge: Intel Corporation 82801 Mobile PCI Bridge (rev e2)

      More details and kernel output is available, if needed.


      The application accesses one addres on a PCI I/O card bytewise (for bitbanging). The relevant driver C-code is rather simple: iowrite8(1, addr);  iowrite8(0, addr);
      All other parameters kept constant, this sequence generates a 0.7us pulse using the older chipset, but 1.2us with the ICH7M . Consequently, the bitbanging is too slow to the data in timebyte acc. The PCI I/O card is the same in both cases.


      Question: Is there any way to configure something in the ICH7M chipset to get a faster single byte, non-burst access (read or write) on the PCI bus ?




        • 1. Re: PCI byte-access latency with ICH7M ?

          I understand you need information about your Intel chipset with ICH7M.

          I am currently researching on this issue. As soon as I can, I will send you a message with my findings. Thank you for your patience and understanding.



          • 2. Re: PCI byte-access latency with ICH7M ?

            Allan, thanks for looking into this.

            Intel doc i-o-controller-hub-7-datasheet.pdf lists the configuration registers, and it would be great to get some help whether the latency of a single-byte read or write to the external PCI bus is in any way influenced by these.

            It seems weird that the Atom/ICH7 combination spends 0.7us more on a bus access than the older 852GM. The read/write seems pretty much an MMU mapped, low level bus access - or is this too naive ?