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The LLC operates on 64 byte cache lines. It can tag 2 lines together for efficiency in rare circumstances, but the basic architecture is 64 byte lines.
Then what's the implication by "in rare circumstances", does it mean that the LLC can work in two modes, or that
most processors tag 64 Bytes but rare processors do 128 Bytes?
And what about the L1 and L2 cache ?
Thank you very much.
It means that in some circumstances, the processor will tag 2 lines at once for efficiency. It is not CPU model specific and is not common.
L1 and L2 always work at 64 byte.