0 Replies Latest reply on Dec 3, 2013 9:59 AM by Nil

    Default memory consistency model of SCC

    Nil

      Hi,

      I have got some questions:

      (i am not using RCCE)

       

      • I am using uncached memory (/dev/rckncm) and I have L2 cache disabled (using SCCGui), in this case what will be the memory consistency model on SCC?

       

      • “Refer to CR0 and the bits CD and NW. Yes, you can disable L1. To do that set both bits to 1. But when you do that, read hits still access the cache and write hits update the cache but not memory. You might argue that this is not really disabling, but it is if you invalidate and flush L1 first. Then, there won't be any read or write L1 hits. You can do this on a page basis with the PCD and PWT bits of the page table entry.”  https://communities.intel.com/message/124955#124955

                Does that mean I have to flush L1 before read/after write even I am using uncached memory? (I am not mistaken in thinking that when I do           mmap using /dev/rckncm, PCD and PWT bits are set/unset correctly)

       

      • Has anyone tried to use SMC for SCC with Linux that comes with sccKit 1.4.2.2 (buildroot 2011.11), as pdf that comes with SMC has examples that worked with buildroot 2011.05, I have tried it with new Linux but sample application (BlackScholes) sagfaults

       

       

      Thank you.