Thank you for the list of ideas. They are very good. You are asking the bare chip to have these interfaces, versus having a small board/package/module that could host such different peripherals? Well, Intel is claiming it will be a synthesizable processor. Take the core, add new peripheral blocks. I am wondering too what the foundry services will be, not sure if anything has been announced.
That leads to another question, what sort of packaging do you envision? Versus what the chip offers now. You do say you want low-pin count packages with leads. All the I/O you want, what's "Low"? I've built 132-pin BGA/TSOP before, that's still huge.
I am sure that someone on the Quark team is scanning these boards, and I hope they can address your ideas better. What's officially on the roadmap and such.
I am saying that many of the ideas I put into my list should be built right into the Quark SoC silicon. This would make the chip much more versitile in low end embedded applications much closer to the way that the AVR's, for example, are built. Packaging can still remain as the BGA as it is today.
The scheme used on the Galileo is a strong attempt to make the Quark fit into the Arduino model but is has some real short comings as well. The slowness imposed by having to use an I2C channel to talk to the I/Os seriously limits the bandwidth available to the pins that is not the same limitation that exists when the AVR processor is programmed to diddle the I/Os.