2 Replies Latest reply on Oct 17, 2013 12:27 PM by m_karas

    More Direct GPIO and OnBoard Peripherals


      The X1000 Quark SoC used on the Galileo board is a great start but there is more that can be done to make this chip family take on the low level embedded space in a more aggressive way. The next chips need to have pin level interfaces that reflect a whole lot more of what simple 8-bitters like 8051s, AVRs and PICs have had for years now...


      Here are some examples:


      1) GPIO's with 5V tolerant inputs

      2) More GPIOs that can be directly bit banged at code execution speed

      3) Onboard timer/counters that include input capture, output compare, and PWM generation capabilities.

      4) Onboard 10 or 12 bit A/D converter that can be driven from muxed analogue inputs

      5) Available analogue comparators that can support triggers to timers or interrupts.

      6) Onboard D/A comverter at 10 or 12 bit resolution.

      7) Onboard DMA channel(s) that can be configured to spew data to/from memory to certain peripherals such as the A/D converter.

      8) Embedded CAN bus controller that supports the HW packet level protocol

      9) Embedded protocol stack for Ethernet in ROM comfigured for network support in fully embedded applications where no OpSys is used.

      10) Low pin count SKUs of the chip in leaded packages for increased ease of use by makers.

      11) Support for very low power sleep modes that support less than microsecond wakeup times.

      12) Enhanced compute architecture that adds DSP primitives such as multiply and accumulate for simple signal processing applications.


      Michael Karas

        • 1. Re: More Direct GPIO and OnBoard Peripherals

          Hello Michael,

          Thank you for the list of ideas.  They are very good.  You are asking the bare chip to have these interfaces, versus having a small board/package/module that could host such different peripherals?  Well, Intel is claiming it will be a synthesizable processor.  Take the core, add new peripheral blocks.  I am wondering too what the foundry services will be, not sure if anything has been announced.


          That leads to another question, what sort of packaging do you envision?  Versus what the chip offers now. You do say you want low-pin count packages with leads.  All the I/O you want, what's "Low"?  I've built 132-pin BGA/TSOP before, that's still huge.


          I am sure that someone on the Quark team is scanning these boards, and I hope they can address your ideas better.  What's officially on the roadmap and such.


          --Richard Vireday

          • 2. Re: More Direct GPIO and OnBoard Peripherals

            I am saying that many of the ideas I put into my list should be built right into the Quark SoC silicon. This would make the chip much more versitile in low end embedded applications much closer to the way that the AVR's, for example, are built. Packaging can still remain as the BGA as it is today.


            The scheme used on the Galileo is a strong attempt to make the Quark fit into the Arduino model but is has some real short comings as well. The slowness imposed by having to use an I2C channel to talk to the I/Os seriously limits the bandwidth available to the pins that is not the same limitation that exists when the AVR processor is programmed to diddle the I/Os.