Encoding of CPUID Leaf 2 Descriptors

[MSAIT7]

Hello.

I got the latest pdf of "Intel(R) 64 and IA-32 Architectures Software Developer's Manula."

Table 3-22 "Encoding of CPUID Leaf 2 Descriptors" says:

Value | Type | Description

4FH | TLB | Instruction TLB: 4Kbyte pages, 32 entries

This description isn't clear whether this TLB is full associative or direct mapping.

Which one? Direct mapping?

And, I found a a typo in the same table. The description of C2H is

"2MBytes/$Mbyte"

This must be typo of 4Mbyte

Thanks.

[Silvia_L_Intel1]

I would recommend you to check Table 3-12 (page 193) and Table 3-17 (page 218) of the "Intel® 64 and IA-32 Architectures -Software Developer's Manual, Volume 2A" for more details. http://download.intel.com/products/processor/manual/325383.pdf http://download.intel.com/products/processor/manual/325383.pdf

Example 3-1 "Example of Cache and TLB Interpretation" explains how to interpret the information about caches and TLBs.

[MSAIT7]

Thank you for your reply.

But...

> Table 3-17 (page 218)

This table describes about CPUID instruction and

it include about EAX=02H. The detail is described in

Table 3-22 as I wrote before.

> Example 3-1 "Example of Cache and TLB Interpretation" explains how to interpret the information about caches and TLBs.

Example 3-1 describes how to parse the result of CPUID with EAX =2.

It describes how to get index values to look up table 3-22 as I said before.

My question is not how to parse CPUID result. Almost all TLB entries in

Table 3-22 describe about the associativity, e.g. direct mapped, {2,4,8,16} way

or full associativity, but some others don't describe about the associativity.

The TLB entires which don't describe the associativity in table 3-22 are:

0x4f

0x50

0x51

0x52

0x5b

0x5c

0x5d

I'm sorry if I'm misunderstanding.