In late October our company plans to release 8Gbit DDR3/DDR3L chips with single-chip-select.
We can then manufacture 16 Gigabyte DDR3 SO-DIMMs as well as UDIMMs with just two ranks.
These DRAMs are organized 1Gx8 and the addressing is exactly per JEDEC: Row-Addresses A0-A15, Column-Addresses A0-A9 & A11, BA0 to BA2.
This addressing is generally supported by any of Intels processors/chipsets that use DDR3/DDR3L, so theoretically I would say this should work, but any datasheet I look at always shows that the max. component size is 4Gbit and max capacity for modules is 8GByte.
Last week we built the first engineering samples of 16GByte modules and tried them on some AMD, Cavium and Freescale platforms. They worked fine. Then we tried on Intel Z77 Express Chipset and it did not work. We looked up the Haswell, Sandybridge, the E5-2600 processor and many others, everywhere it says max 8GB per module and max IC capacity 4Gbit.
I noticed that several Apple Macbooks using Intel processors claim the max capacity would be 32GB, but these only have 2 sockets. When I check the spec for the processors used here, I read again: Max 8GB per module.
All this is confusing as the address lines are definitely there, so why should you limit your processors and chipsets?
Coiuld you please investigate here?