4 Replies Latest reply on May 30, 2013 11:39 AM by Misiu

    What is the Memory to L3 Cache mapping function for Nehalem Architecture (Xeon X3430)


      Hello Community,


      I am a a researcher working with the mappings from physical memory to the shared L3 cache on a Xeon X3430 processor.  We purchased the X3430 specifically because the Nehalem architecture (unlike Sandy Bridge) has no mention of sectioning (slicing) the cache and would imply a direct mapping from memory addresses to cache lines.


      Our experiments, and some new-found documentation, implies that this may not be the case.  Images of the processor, as well as minor mentions in some documentation, suggests that the L3 may be sectioned, which would imply some sort of novel mapping.


      Would anyone have any information regarding how the L3 cache in Nehalem processors would map memory?  Sandy Bridge is documented as using a simple hash function (although it does not specify the function).  So long as we know how to predict which cache lines are mapped to which memory addresses (and vice versa) we can incorporate it into our experiments and get everything back on track.


      Alternatively, if anyone can put me in direct contact with an Intel Engineer (I have had no luck through conventional channels) it would be much appreciated.


      Thanks for the help.