I found BIOS setting information on NTB_s2600jf_r1_4.pdf. There are many NTB setting in BIOS Adavance->PCI configuration menu. But in my BIOS there is nothing about NTB. My BIOS version is SE5C600, 01.08.0003, build date 02/26/2013 15:21:51
This option is very specific to the hardware configuration of the S1600JP/S2600JF/S2600CO/S2600WP board, and appears only for those boards.
Yes, I understand the NTB is a very specific function. So I confirmed with the sales that the R1000GZ/GL must support the NTB function. The answer is positive so I buy the two server. I read many documents and all of them say the R1000GZ/GL supports NTB, doesn't it?
I check the document of R1000GZ/GL, the board is S2600GZ/S2600GL. So the R1000GZ/GL has no change to support NTB function? The only way is to change board ? Thanks for your help!
I checked the TPS, and NTB is mentioned once. I'll dig around and find out more information.
I verified, NTB is *not* supported on the Intel Server Board S2600GZ/S2600GL Family, which is used inside the Intel Server System R1000GZ/GL Family
Thanks! I will change to the following board, it supports NTB ?
Intel® Server Board S1600JP4
8 DDR3 ECC UDIMM 1333, RDIMM 1600, LRDIMM 1333
Supports up to 4 hot-swap 2.5" or 3.5" drives
750W AC, Platinum Efficient
Yes, that list of boards I mentioned above, S1600JP/S2600JF/S2600CO/S2600WP, the one you are looking at is the S1600JP.
Pay attention it's a full system, not a board, so you need S1600JP based system (like R1208JP...)
Hi Dan_0 and Saar Blitz,
Does S2600CP family also support NTB? Thank you.
No, not the S2600CP. Only the:
Those two letters at the end, tell you which product family. If your product doesn't have JP, JF, CO, or WP in it, then it does not support NTB.
Hi Dan_0 and Saar Blitz,
I want to purchase a INTEL server with the following capability,
1. There are two PCIe adapters pluged in the server
2. The PCIe adapters will read/write the memory in the other adapter through DMA
3. The most important is that the IOMMU is enabled.
As my understanding,
When the IOMMU is enabled, all the PCIe TLP transaction will go to the IOMMU to check the authority.
The adapters access the DRAM is OK, the TLP path is OK from adapter to IOMMU then go to DRAM.
But when adapter A tries to write a data into adapter B's memory, the TLP should go to IOMMU and then go to adapter B.
In this case, there should be one PCIe bridge behind IOMMU to handle the TLP, let it resend to adapter B.
I can not find any information about the relation of IOMMU and PCIe root complex.
I don't know which INTEL server can support the case 2.
Please give me the server model name or where I can get more information about my requirement.
Thank you very much.