1 Reply Latest reply on May 1, 2013 6:25 PM by sylvia_intel

    tsc failures w/ BOXDX79SR with Linux

    Michael Sartain

      We put together a machine at work here with the DX79SR motherboard, and we are getting the below tsc calibration errors. We've tried this with BIOS versions 494 and 559 with the same results. This is running 64-bit Ubuntu 12.04. Right after booting we see this:

       

      mikesart@mikesart:/sys/devices/system/clocksource/clocksource0$ dmesg | grep -i tsc

      [    0.000000] Fast TSC calibration using PIT

      [    0.296446] TSC synchronization [CPU#0 -> CPU#1]:

      [    0.296449] Measured 241647156 cycles TSC warp between CPUs, turning off TSC clock.

      [    0.008000] Marking TSC unstable due to check_tsc_sync_source failed

       

      mikesart@mikesart:/sys/devices/system/clocksource/clocksource0$ cat available_clocksource

      hpet acpi_pm

      mikesart@mikesart:/sys/devices/system/clocksource/clocksource0$ cat current_clocksource

      hpet

       

      The end result of this is that rdtsc isn't synchronized across cores and it breaks several profiling applications. Ie, we'll see 0x000814e0586a436c followed shortly thereafter by 0x000006674d9a4254 when the thread gets moved to a different core. (Time just went backwards in a big way).

       

      My understanding after talking to some open source kernel folks is that this is potentially an issue in the bios (see below). Has anyone else run into this issue? How would we go about trying to get in touch with some folks at Intel that could possibly help investigate / fix this issue?

       

      Thanks much.

      -Mike

       

      ----- from kernel person -----

      so the way the hardware works is that there is 1 "master" tsc in the CPU package, that gets started when the cpu package comes out of reset. all logical cpus keep an offset value from that, which starts at 0, and the "master + offset" value is what gets returned on rdtsc. if someone writes to the tsc (using an MSR), what actually happens is that the master tsc does not change, only the per logical cpu offset gets changed.

       

      Linux does not write to the TSC since quite a while... which means the BIOS is doing that. It really should not.

       

      Some bioses write to the TSC to "hide" the cpu cycles used in SMM from the OS..... maybe that is going on here.