0 Replies Latest reply on Jan 11, 2013 9:26 AM by Tom

    How to receive L1, L2 & L3 cache size using CPUID instruction in x86

    Tom

      Hi there,

      I encountered a problem during preparing an assembler x86 project which subject is to write a program getting L1 data, L1 code, L2 and L3 cache size. I tried to find something in Intel Documentation & in the Internet but I failed. THE MAIN PROBLEM IS:  In case of AMD processors it is just to set EAX register to  80000005h & 80000006h values and get desired data from ECX and EDX registers but in case of Intel I can obtain this information only for L2. Can anyone help me and tell me what should I do to get L1 & L3 cache size for Intel processors ?

       

      Thank you in advance.

       

      Kind regards,

       

      Tom