How to receive L1, L2 & L3 cache size using CPUID instruction in x86

Processors

Intel® Processors, Tools, and Utilities

How to receive L1, L2 & L3 cache size using CPUID instruction in x86

1,270 Views

Hi there,

I encountered a problem during preparing an assembler x86 project which subject is to write a program getting L1 data, L1 code, L2 and L3 cache size. I tried to find something in Intel Documentation & in the Internet but I failed. THE MAIN PROBLEM IS: In case of AMD processors it is just to set EAX register to 80000005h & 80000006h values and get desired data from ECX and EDX registers but in case of Intel I can obtain this information only for L2. Can anyone help me and tell me what should I do to get L1 & L3 cache size for Intel processors ?

Thank you in advance.

Kind regards,

Tom

Link Copied

0 Replies

Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.