Yes, it is PLRU: Three-LRU bit in specific.
Wait, I just found a problem. How do you use 3 LRU bits to handle 16-way set associative L3 slices? I previously thought you were referring to using 3 bits in a 4-way set associative similar to SCC L2. (http://communities.intel.com/servlet/JiveServlet/previewBody/5753-102-1-8879/L2cache.pdf)
Is it just a similar implementation where you use 5 bits to walk the tree?
You may want to post this query to the Intel(R) Software Network forums: Forums | Intel® Developer Zone
I am escalating this internally to see if this information is available through this support channel; still, please contact the Software Network forums.