I am observing timing behaviour on the SCC (baremetal) that I need help understanding:
A process on Core 14 sends a message to Core 28, Core 18, Core 02, Core 40 (in this order). The message is 16 bytes long.
Here is what I observe:
(1) Core 02 gets the message in ~2300 clock cycles;
(2). Core 18 gets the message in ~4600 clocks cycles;
(3). Core 28 gets the message in ~6900 clock cycles;
(4). Core 40 gets the message in ~2100 clocks cycles;
I wonder why Core 28 takes so long to receive the message, and I would expect that it would receive the message *earlier* than Core 40 (XY routing).
I am assuming it has something to do with wavefront arbitration at the router. I found a document that talks about it, but am still confused.
Can anyone see what is going on?