5 Replies Latest reply on Sep 6, 2012 5:25 PM by vjain27

    Inter-processor interrupt on SCC

    vjain27

      Hi,

       

      I am trying to figure out how to send an IPI from one core of SCC to another. I found from the post - Sending an interrupt to another core.  that by writing to the core configuration register of a core an IPI can be sent to it but I am not clear about how to handle the IPI as there is no place to

      specify for the vector number of the interrupt. Please tell me what vector number should I use for writing an ISR for the destination core.

      (The P54C manual mentions that IPI can be sent by writing to ICR whose first 8 bits are for specifying vector number but the core configuration register doesn't seem to have to these bits )

       

      Thanks

      Vaibhav Jain

        • 1. Re: Inter-processor interrupt on SCC
          darence

          Using the off-chip GIC (global interrupt controller) is your best bet. See Section 5.3 of this document: sccKit140_UsersGuide_Parts1-7.pdf

           

          The GIC approach is much more flexible than writing to the core configuration registers directly. You can check the source of an interrupt, send interrupts in parallel etc.

          1 of 1 people found this helpful
          • 2. Re: Inter-processor interrupt on SCC
            JanArneSobania

            Hi,

             

            the local APICs of the GaussLake cores (modified P54C used in the SCC) are not connected to an APIC bus, so they cannot communicate with each other. You cannot use the local APIC to send an IPI to another core.

             

            To send IPIs, you have two options:

            1. Control the destination core's LINTx pin directly, by writing to its CRB.
            2. As darence suggested, use the global interrupt controller.

             

            Please note that in case 1, you need to coordinate access to the CRB if two cores want to send IPIs to the same destination concurrently. As far as I know, there is no reliable method to do this if the global interrupt controller is enabled as well. Please also note that the EMAC interface in interrupt mode utilizies the global interrupt controller, so I strongly recommend not to write to the CRBs yourself (at least not as part of normal system operation) if you are using the EMAC interface.

             

            In both cases, to receive IPIs, you must configure the corresponding LINTx input(s) of your local APIC to use FIXED mode. In SCC Linux, the LINTs are already configured to route incomming interrupts to Linux IRQs 3 and 4 (you do not need the vector number here, as that's handled by the kernel). If you write your own operating system, you can use any vector number you like (as usual, avoid the first 32 vectors because they are reserved for exceptions).

             

            If you are using the global interrupt controller, all the interrupts it takes care of (peripheral/EMAC, IPIs and MCPC) come in via a single LINTx pin (you can choose which one you want it to use via a configuration register). All demultiplexing must be performed in software. Device drivers therefore need to share the vector; and if their handler gets called, check at the global interrupt controller whether it was their device the interrupt was sent for.

             

            Regards,

            Jan-Arne

            1 of 1 people found this helpful
            • 3. Re: Inter-processor interrupt on SCC
              vjain27

              Thanks for the explanation! But I need to clear a few details. I am currently writing my own kernel and

              want to send IPI from one core to another. As far as I have understood from your reply and by reading the docs ,

              for the first method (writing to CRBs) here is what needs to be done :

               

              - Configure LINTx pin of the local APIC of the destination core by writing to the LVT register. From the manual I could see that I can specify a vector number for a LINTx pin. I guess this would be the vector number of any interrupt coming to that particular LINTx pin.

               

              - Write to core configuration register of the destination core to generate an IPI.

              But I am confused about how to specify in the core configuration register which LINT pin (LINT0/1) to send the interrupt to. In the EAS I can only see three bits of use - bit 0 , 1 , 2 which specify whether to generate NMI, INTR or INIT.

              Please clarify.

               

              Thanks

              Vaibhav Jain

              • 4. Re: Inter-processor interrupt on SCC
                JanArneSobania

                - Configure LINTx pin of the local APIC of the destination core by writing to the LVT register. From the manual I could see that I can specify a vector number for a LINTx pin. I guess this would be the vector number of any interrupt coming to that particular LINTx pin.

                Correct. If you set the vector number of the LVT register for LINTx to y, and the delivery mode to "fixed", you get an interrupt on vector y when the LINTx pin is asserted. Please note that you need to set the delivery mode correctly; you can use either "fixed" or "NMI" on the SCC. "ExtINT" does not work here because there is no 8259A-compatible interrupt controller attached to the core.

                 

                It is strongly suggested to use an interrupt vector of 32 (0x20) or above. The first 32 vectors are reserved for processor exceptions.

                 

                - Write to core configuration register of the destination core to generate an IPI.

                But I am confused about how to specify in the core configuration register which LINT pin (LINT0/1) to send the interrupt to. In the EAS I can only see three bits of use - bit 0 , 1 , 2 which specify whether to generate NMI, INTR or INIT.

                The three bits you mentioned directly control the corresponding pins on the processor core. The terminology is the same as for an APIC in "virtual wire" mode: LINT0 is INTR, and LINT1 is NMI. For more information on the APIC, I recommend the Intel MP Specification in addition to the processor manual.

                 

                You may also want to have a look at the SCC Linux source code on https://github.com/hpi-scc/. The APIC is setup in the routine scc_setup_local_APIC_LINT in https://github.com/hpi-scc/linux-kernel/blob/scc/arch/x86/platform/scc/scc.c. The routine sccsys_trigger_irq_direct in https://github.com/hpi-scc/linux-kernel/blob/aa243173f471da427d177c9b85196ba0f53ae932/drivers/char/sccsys.c shows how to send an interrupt by asserting on of the LINT pins directly.

                 

                Regards,

                Jan-Arne

                • 5. Re: Inter-processor interrupt on SCC
                  vjain27

                  Thanks a lot! Finally got it to work!