I am interested in investigating the SCC's L2 cache sleep states. I have read multiple times on MARC posts and in documentation from Intel that the L2 caches can both be turned off/on and be put into sleep states. Could someone elaborate on what registers I need to turn the L2 caches on and off as well as into sleep states?
Furthermore has anyone already explored this area and determined the possible power savings from L2 cache sleeping? And does anyone know how long it takes the L2 caches to go from off / on or from sleeping to awake?