1. They are bidirectional. Routing is deterministic, XY to be more precise. This means that, on the path from the source to the destination tile, you first completely traverse the x axis, and then the y axis. As a consequence, when a packet travels from core A to core B, it traverses a different set of routers than when it travels from B to A (unless A and B are in the same row or column).
2. You just go to the closest memory controler to your tile.
3. No, the routes are fixed as described under 1).
Hope this helps.
If you could provide one more clarification that would be great.
The connectivity of the routers at the edges of the mesh is not clear to me yet. If you consider routers 1,2,3,4,5,6 in that order from left to right, are router #1 and router #6 one hop away? I mean do they wrap-around? Similarly I've question about the routers at the edges of all the columns.
I suspect that the answer to that is a No looking at the pictures of the Intel SCC mesh topology. However, the description of the wrapped wavefront arbiter confused me a bit.
Nope, there's no wrap-around. To go from #6 to #1 in your example you have to traverse all the routers in between.