TLB entries, page faults and cached paging structures

[idata]

Hi,

I have a few questions on which I was not able to find consistent answers in the Intel specs and/or on the web.

It would be great if someone could help me out with them:

- in general a TLB entry is created after a successful address translation. however, does this also happen if the resulting memory

is not accessible due to access protections (=> page fault)? I mean: the address translation itself worked properly ...

- is an existing TLB entry invalidated if a page fault occurs for that address? Is there different behavior for a) no memory mapped

or b) an access protection occurs ?

- besides the TLB entries: are the PDE/PTEs also stored (as regular data) in the L1/L2/LLC Caches? Or is there an additional cache

for the paging structures?

- if so: are there any circumstances under which the MMU flushes already cached PDE/PTE entries from the L1/L2/LLC caches?

Thanks a lot for your help in advance ...

cw

[idata]

If you are interested in obtaining this information, we would recommend you to contact a Field Application Engineer (FAE) at one of our distributors.

A list of our distributors can be found at the following web site:

http://locate.intel.com/ http://locate.intel.com/

Once you get to this site, select the country, your location and you will receive a list of our distributors to find one that is located in your area.