1 Reply Latest reply on Mar 8, 2012 1:06 PM by Adolfo_Intel

    Machine check exception decoding information

    lanzaro

      I'm Anna Lanzaro, a PhD student of the University of Naples doing some
      research about the Machine Check Architecture (MCA). I was wondering
      whether you have some information about the correspondence between the
      banks of the MCA and the hardware units they are related to. I was
      reading the Intel documentation about how to decode machine check
      errors ( Intel® 64 and IA-32 Architectures Software Developer’s Manual
      Volume 3 System Programming Guide
      http://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-software-developer-system-programming-manual-325384.html).

      For example I saw that MC8_STATUS may be related to the memory
      controller, but I don't have this information for the processor i7
      Sandy Bridge family 06_2AH and I didn't find any documentation at all.

      Please, could you tell me how all the MCi_STATUS (i=0,1...8) registers
      map each hardware units on my processor and how I can decode them?

       

      Anna