Does anybody knew about the failure nature and rate in on chip memory (which is called MPB in SCC case)? Is there any detection and correction mechanism for failures on MPB? We understood the error detection and correction on the network on chip, but when it comes to MPB we were not able to find such a mechanism based on the Intel documents.
The only information I've been able to find is EAS:6.4. This section says that the MIU checks for parity but attempts no error correction on mesh packets. It says it retries on error and that the number of retries is programmable. I'll see if I can find out something more detailed ... like if there is any information on failure rate and how one might program the number of retries.