The subject of this post is on slide 9 in http://communities.intel.com/docs/DOC-5175
It is followed by, "Solution: Don't. Always push whole cache lines." I didn't get to see this presentation, and I do not understand what these two lines mean. Can someone please explain them?
This thread goes into quite some detail:
In short, to write through to MPB, you need to make sure that the write doesn't get delayed due to write-combining. So either write a whole cache line, or perform an additional dummy write to a different cache line so that the contents of the write combine buffer are flushed to MPB. Note that this assumes that the data is not present in L1.