1 of 1 people found this helpful
Basically you can't use it, or perhaps when only one of the two cores on the tile would use the MPB.
Unfortunately, there is an arbitration bug when both cores access the MPB: http://communities.intel.com/docs/DOC-5405
It has a great advantage if it could be used, as it makes MPB accesses as fast as the L1 cache, about twice the speed you get from MPB access without the bypass bit. An interesting thing we noticed while trying the bit out is that the whole LUT entry seemed to be ignored when the bypass bit was set, all requests would go to the MPB even if a completely different (or invalid) destination was specified. However, when you attempt to access beyond the 16KB of the MPB your core would freeze. Proceed with caution, probably you really dont want to use it, unless you are completely sure that the situation can't occur.