0 Replies Latest reply on Jul 28, 2011 4:28 AM by Kunalnitin

    Delayed TLB invalidation in Intel processors

    Kunalnitin

      This in reference to InteI's Software Developer’s Manual (Order Number: 325384-039US May 2011), the section 4.10.4.4 "Delayed Invalidation" describes a potential delay in invalidation of TLB entries which can cause unpredictable results while accessing memory whose paging-structure entry has been changed.

       

      The manual says ...

      "Required invalidations may be delayed under some circumstances. Software devel-

      opers should understand that, between the modification of a paging-structure entry
      and execution of the invalidation instruction recommended in Section 4.10.4.2, the
      processor may use translations based on either the old value or the new value of the
      paging-structure entry. The following items describe some of the potential conse-
      quences of delayed invalidation:
      • If a paging-structure entry is modified to change the R/W flag from 0 to 1, write
      accesses to linear addresses whose translation is controlled by this entry may or
      may not cause a page-fault exception."

       

       

      Let us suppose a simple case, where a page-strucure entry is modified (r/w flag is flipped from 0 to 1) for a linear address and after that the corresponding TBL invalidation instruction is called immediately. My question is--as a consiquence of delayed invalidation of TLB s it possible that even after calling invalidation of TLB a write access to the linear address in question doesn't fault (page fault)?

       

      Or is the "delayed invalidation" can only cause unpredictable results when "invalidate" instruction for the linear address whose page-structure has changed has not been issued?