Yes, there is a difference in latency. All bus accesses of the cores are mapped to a pair of messages on the on-die network. The latency of an individual access then depends on the number of hops these messages need to arrive at their destination.
The number of cycles (split into tile and bus cycles) is documented in the EAS. If you are interested in bandwidth, you can find some benchmarks in the slides from the March 2010 symposium (http://communities.intel.com/docs/DOC-5902), page 13.
Thanks for the reply. The info is very useful.