5 Replies Latest reply on Jul 20, 2011 9:18 AM by jheld

    Details on communication

    MarcBoyer

      Dear all,

       

      I have read a few documentations, and I have a few questions on the SCC Mesh.

       

      1) Each Tile router have a 5-port cross-bar router, with 8 virtual channels (ie 8 FIFO queues ?), and a WWFA arbitration. What is the depth of each virtual channel ? How is chosen the virtual channel for each Flit ?

       

      2) The low-level communication paradigm is to have a blocking RCEE_send. But with a packet/Flit switch, there is no need of blocking communication. So, is there an implicit wormhole routing algorithme in the mesh ?

       

      3) Is there a way for the programmer to influence the router behavior ? Consider the case where processor 0 send messages to processor 4. It will cross the tile of processors (2,3). Is there a way to influence the behavior of this tile ?

       

      Regards,

        Marc Boyer

        • 1. Re: Details on communication
          Hayder

          Hi,

           

          Did you read this paper (A 2 Tb/s 6     4 Mesh Network for a Single-Chip Cloud Computer With DVFS in 45 nm CMOS)?

           

          Regards

          1 of 1 people found this helpful
          • 2. Re: Details on communication
            MarcBoyer

            No, was not aware of this paper. I have just downloaded it, and even if it is a bit short (2 pages), it contains some answers, and, moreover, its gives references to others papers. I am going to read it all.

             

            Thank you.

            • 3. Re: Details on communication
              Hayder

              Hi,

               

              Actually, this paper contains 10 pages. Should you downloading this paper from IEEE website.
              I am sure, you will get answers for your questions.
              Good luck
              • 4. Re: Details on communication
                MarcBoyer

                OK. In fact, there are two papers with similars names: one 2 pages long, published in IEEE Symposium on VLSI Circuits (VLSIC), 2010 and another, 10 pages long, published in IEEE journal of solid-stae circuits. I have made the confusion between both.

                 

                Thank you.

                • 5. Re: Details on communication
                  jheld

                  1) Each Tile router have a 5-port cross-bar router, with 8 virtual channels (ie 8 FIFO queues ?), and a WWFA arbitration. What is the depth of each virtual channel ? How is chosen the virtual channel for each Flit ?

                   

                  The journal paper describes the design fully (IEEE Journal of Solid-state Circuits, vol 46, No4, Aprill 2011.)

                   

                  2) The low-level communication paradigm is to have a blocking RCEE_send. But with a packet/Flit switch, there is no need of blocking communication. So, is there an implicit wormhole routing algorithme in the mesh ?

                   

                  The blocking behavior of RCCE_send is not related to the router.  There is a community contribution called iRCCE that provides non-blocking asynchronous calls .  See http://communities.intel.com/message/110482#110482

                   

                   

                  3) Is there a way for the programmer to influence the router behavior ? Consider the case where processor 0 send messages to processor 4. It will cross the tile of processors (2,3). Is there a way to influence the behavior of this tile ?

                   

                  No.  Router operation is fixed and presented to the Cores via a memory load/store abstraction.   Only the management console PC software can send and receive packets.