I don't know well about interrupt mechanism in hardware.
I tested interrupt behavior with some modification in SCC Linux.
What I found is that the interrupt-disabled core cannot get an interrupt.
Let's think about the scenario.
1. Disable core 0's interrupt
2. Core 1 send an interrupt to core0.
3. Enable core 0's interrupt
In this case, core 0 can get an interrupt generated by core 1?
In my example code, it is not true. Could anyone tell me the detail operation of the hardware mechanism about interrupt?
One more thing, what can I do in this case?
Should core 1 generate an interrupt message again and again until core 0 get this?
Thanks. Junghyun Kim.
Yes, I actually implement an interrupt module with the code drivers/net/rckmb.c
It is worked very well with two cores, but when it comes to four cores, sometimes a core misses the interrupt.
I don't know the exact reason why it is not working.
I'll look into the code again.
The interrupt hardware is fully documented in the Pentium manuals in the documents section.
The register connects to the signals of the Local APIC. There is no IO APIC or APIC bus.
If you are running sccKit 1.4.0 FPGA bitstream then you may want to use the new IPI facility.
See the User Guide for 1.4.0 in the Documents section. It provides a more conventional interrupt controller.
I am trying to use the Global Interrupt Controller Registers that come with the new IPIC facility, each core can set its own request registers and this is reflected in the status registers, however the intercore request register writes are failing. Any help is highly appreciated