2 Replies Latest reply on Jul 8, 2011 1:24 AM by Enric

    L2 sleep state



      I've seen that the L2 has a sleep state able to reduce the voltage of the cache.

      Does someone know if for lower voltages is still possible to read or write them or this modes are only intended to preserve the data at a lower energy cost (like Drowsy caches)?


        • 1. Re: L2 sleep state

          That bbl2slppgm setting in EAS:Table 9 ... it really wasn't intended to be exposed. But it is what you suspected. It determines the L2 retention voltage, which is the voltage used when the cache is not accessed. When not accessed, the cache goes to sleep at the retention voltage (hence reducing leakage), but normal voltage resumes on access.  One cannot really access the cache data at the reduced voltage ... it is as you said a drowsy cache.


          The 1111 (the default) is the safest setting. If you change this value, you will reduce the retention voltage (and consequently leakage). Another setting, however, may end up actually changing the tile frequency. You then won't really know what frequency the chip is running at. The possiblity exists of putting the chip into an unsafe state.

          • 2. Re: L2 sleep state

            Thank you, that is what I wanted to know.