0 Replies Latest reply on Jun 29, 2011 5:12 PM by cbf123

    why is Cave Creek needed for asynchronous DRAM refresh?


      I'm looking at the Sandy Bridge EP, and a few places have indicated that the Cave Creek chipset is needed for async DRAM refresh.


      Given that the memory controller is in the CPU itself, this seems sort of odd.  Is this an artificial limitation to the Patsburg, or is there a real technical reason why the chipset needs to be upgraded to support it?