I don't understand how the legacy irq generated from an endpoint attached to one of the 8 pciexpress port is routed to the PIC.
I found register to route the pci pirqn# to PIC lines, and other registers to route internal functions to PIC lanes.
But nothing to decide, for example, how the "intan" of pciexpress port 1 became (it seems) "pirqa#" and then "irq5" of the PIC. Is it a fixed routing or there is something I missed?
Really thanks for any help,
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