I passed your question on to one of our hw designers. Basically the response is that comparing data with McPAT is problematical. Here's the quote...
Although McPAT can be a good architectural exploration tool when it comes to correlating with real die area for SCC is hard.
For example the Memory controller was floorplanned to fill up the remaining space. It has empty spaces with fillers. It also has digital control blocks that are specific to the SCC implementation and is not a part of the typical memory controller so off the shelf area estimator won’t work that well.
Would knowing the chip area of the power domains help?