1 Reply Latest reply on Jun 20, 2011 12:01 PM by tedk

    Area and Power Modelling of SCC chip with McPAT


      Hi All,


      McPAT is an integrated power, area,             and timing modeling framework for multithreaded, multicore, and manycore architectures. It is now is a part of HP lab  free products.


      I have tried to model SCC chip with McPAT.

      This is done thorugh making an XML file that contains all of the parameters related to different parts of SCC architecture.

      for example, total number of cores, size and number of caches, number of memory controllers, structure of NOC and so on.


      After that, McPAT analazes the XML file and generates a report. The report contains "Estimated" values for area and power consumption of the chip.

      At current stage of development, I get good numbers for power consumption on the chip.

      But for area, the estimated area by McPAT is different with what reported for SCC chip in Intel's report.


      My reference for obtaining the area of each of the SCC sections is this paper: "A 48-core IA-32 Message-Passing Processor with DVFS in 45nm CMOS"


      example: from the above paper i conclude that the area consumed by each of the memory controllers in SCC is approximately 20mm2

      However the estimation of McPAT is different. ( much smaller)


      More over, I have been told that, SCC chip layout is not optimized for area and it has some areas with no logic inside.


      My question is:

      Does any body know about the real area consumption of different sections of SCC chip? Is there any other reference for this information than the paper that I am using? (for now we can just consider the memory controller modules.)



        • 1. Re: Area and Power Modelling of SCC chip with McPAT

          I passed your question on to one of our hw designers. Basically the response is that comparing data with McPAT is problematical. Here's the quote...

          Although McPAT can be a good architectural exploration tool when it comes to correlating with real die area for SCC is hard.


          For example the Memory controller was floorplanned to fill up the remaining space. It has empty spaces with fillers. It also has digital control blocks that are specific to the SCC implementation and is not a part of the typical memory controller so off  the shelf area estimator won’t work that well.

          Would knowing the chip area of the power domains help?