Since the L2 is external in that Pentium generation the performance counters don't comprehend it.
Differencing the pipeline stall times with L2 enabled and disabled may give you some indication of its impact for the workload.
Perhaps something else indirect may be possible, depending on what you are trying to do.
Do you think it is possible to measure the performance of the network (router)? For example measure the congestion.
Sorry, no. The cores don't have access to the mesh network internals.
Does the FPGA have access to the mesh internals?
I am also looking to do some measurements, which involves counting L1 and L2 cache misses. I see that you asked this question a while ago.
Could you find any reasonable approach that seems to have answered this question?
Thanks a lot.