It happens to me on the same board with the exact same latest BIOS. We need to disable L0s for debugging on that platform. But in PCIe trace, it shows FTS order set was conducted and L0s cannot be disabled on root complex 00:03.0 even PCIE ASPM L0s was set to DISABLE in system BIOS. In ASPM control bit on root complex 00:03.0, it is always set to 01b.
I found a workaround which is acceptable in our application.
We develop PCIe adapters. Our PCIe endpoint controller has some issues with ASPM L0s support.
We thus have to disable it on the host platform. It should be possible in the BIOS, except in WX58BM due to the bug I explained before.
So we found here another way to disable L0s : http://www.xilinx.com/support/answers/36325.htm .
We set Ls exit latency and acceptable latency to non achievable settings for the host. => host desactivates ASPM L0s
I have tested it on WX58BP and it works fine.
Hope this helps,
Thank you, Pierre.
We also find a workaround to avoid it. We can just set the ASPM Control Bit to 00b for root complex after BIOS post. In this way, ASPM L0s and L1 are disabled. And it works for our PCIe adapters as well. I can try your way in my side.
It seems this issue is related to Intel BIOS. It should be fixed.
Anyway, Pierre, thank you all the same.