Core i7 920 IMC register programming

[idata]

Hello Everyone,

920 processor is running Linux OS, and I would like to change the configuration value of IMC (Integrated Memory Controller) registers. When I looked at the datasheet of the processor, the concerned registers are RW type. However, any writing trials failed to update the previous value. Even if there was no error for this write, the old value in a register keeps alive across update operaton. Do you have any idea how I can write some values to IMC configuration registers in Core i7 920 processor?

Thanks for any comment on this in advance.

[idata]

Well, this is a simple question... not. Can you be more specific regarding which registers you are interested in, since there are few generalities regarding them. Which Device and Function numbers do the registers belong to? Which ones are not cooperating? The individual bits or bit pairs, etc, within a register can have an attribute/type assigned to them, such as RW or WO, which is very common, more so than the entire register being RW.

How are you testing your writes, with a read, write, read sequence? Are you verifying your masks and LSB-MSB sequence? Basic stuff, I know, but the slightest thing wrong at this level and all is lost.

[idata]

Parsec,

Best of all, thanks for your reply.

>Well, this is a simple question... not. >Can you be more specific regarding which registers you are interested in, since there are few generalities regarding them. >Which Device and Function numbers do the registers belong to? >Which ones are not cooperating? I tried to update several registers having RW attribute. For example, MC_CHANNEL_0_ROUND_TRIP_LATENCY register (device 4, function 0, offset D4h, Access as a Dword) is among them; You can refer to the page 78 of processor datasheet (Document number: 320835-003). >The individual bits or bit pairs, etc, within a register can have an attribute/type assigned to them, such as RW or WO, which is very common, more so than the entire register being RW. I cannot see such bitwise attributes from the official datasheet of 920 Series. If there are those attributes, please update your datasheet. >How are you testing your writes, with a read, write, read sequence? Are you verifying your masks and LSB-MSB sequence? Basic stuff, I know, but the slightest thing wrong at this level and all is lost. I wrote a simple device driver to access those pci devices, and was using Linux kernel's PCI API family to read from or write to the registers. I tested with both endianness, but they were futile.By the way, what do you mean with masks? Can you say this a bit more? The official datasheet doesn't specify the specific mask register, but I am guessing there may be such a mask register to unlock writes to the concerned registers. In summary, I would like to hear whether or not you can write to the above example register (i.e. MC_CHANNEL_0_ROUND_TRIP_LATENCY). Especially, I want to know if you had to unlock the write operation by setting another register prior to updating the example register.Thanks.