6 Replies Latest reply on May 8, 2011 2:33 PM by ziyad

    LUT control to isolate cores?




      I am running some applications on the SCC to see the reliability of the cores at different VF points. However, we realized that when a core goes down (crashes), it can corrupt some other information in memory that it has access to and as a result take down several cores with it.


      During the symposium we talked to one of the organizers (Jim) and he assured us telling us that there is a way to control the LUTs of the different cores to make them unaware of the existence of the other cores and limit their access to critical regs/memory locations.


      Do you know how we can modify the LUTs for this purpose so that we can run our applications and when a core goes down it won't touch other cores?



        • 1. Re: LUT control to isolate cores?

          You'll need to read the EAS in detail (http://communities.intel.com/docs/DOC-5044) and it may be useful to read the presentations on sccKit and sccMerge in particular, e.g. http://communities.intel.com/docs/DOC-5847  You'll need to use a baremetal environment, such as that provided by Microsoft (http://research.microsoft.com/en-us/downloads/37ccb116-c67d-4c44-9181-898889b8352d/)  or RTI (http://communities.intel.com/docs/DOC-5913).

          LUTs form a table with entries that control the physical to physical address mapping - 32b core physical to 64b system physical addresses.  The table is part of the configuration register space that is itself mapped by a LUT entry.  A core can access its own or any other core's LUT and therefore control the mapping seen by other cores.  If you write code that doesn't use CRB space while running (no Interrupts for example) then it could run in a private physical address space and not be able to change it.


          A master core would set the mappings to give it a private section of physical memory and configure its CRB.  The slave core, without the ability to access the CRB could not change that or 'see' any other addresses on the system.  The master core could, by contrast, oversee the private memory of the core and through its CRB reset, start or stop it.  Through a designated location the master could see that the private core continues to execute accurately (or not).  The master can vary the V or F of the region the slave core is in to introduce failures.


          • 2. Re: LUT control to isolate cores?

            I have another question while I go over documentation.


            You mentioned that we have to use a BareMetal environemnt. But I was wondering if we can do this and load linux. Is there a way to tell the re-initialization process to map the LUTs specifically for each core so we can load linux images onto the cores.



            • 3. Re: LUT control to isolate cores?

              Yes, the files that control how LUTs are configured could be modified by hand to do that, or modify once running.

              The question is can you get Linux to run without access to the configuration register block.

              Take a look at what is in the CRB space and what is used by the drivers.

              Or dynamically change that LUT entry and see if it crashes.

              • 4. Re: LUT control to isolate cores?

                Hi Jim,


                Thanks for your help.


                We are now currently working on the MS baremetal environment and I want to go ahead and do the isolation I mentioned in the earlier post.

                I read the EAS and have a good idea on how the LUTs function, yet I could not actually achieve what I wanted to do. I am aware that the GUI provides an option of loading a LUT config file (.dat format) and was wondering whether this is the way to do it. If yes, then I need some sort of direction on where to find the default file and how to edit it. If not then I am not sure how to block LUTs from a core.


                Also, is it possible to use RCCE on baremetal (maybe with some modifications)? If not what is the cleanest alternative and where can I find documentation?


                Thanks again.

                • 5. Re: LUT control to isolate cores?

                  Just to get some background on what you are doing ...

                  Did you get the latest MS Visual Studio plugin from http://research.microsoft.com/en-us/downloads/37ccb116-c67d-4c44-9181-898889b8352d/ ?

                  Is that what you mean when you say you are running the MS baremetal environment? Can you succuccesfully run the TestPrintf function that comes with that download?


                  Are you running sccTcpServer on your MCPC? Where and when did you get the copy of sccTcpServer?

                  • 6. Re: LUT control to isolate cores?

                    I got the latest MS Visual Studio plugin from the link you provided.


                    I can successfully run the TestPrintf (using the Cirque terminal).


                    I am running sccTcpServer on my MCPC. I got it from the newer sccKit 1.4.0 files repository.