You can turn off a core's clock completely by setting its STPCLK# bit to 0. The bit is located in the configuration register, bit 6; EAS version 1.1, page 19, table 7: control portion of the core configuration register.
However, please note that this setting is overwritten by crbnet (Ethernet over PCIe) when sending a packet from the MCPC to the core. I think there is also a race in rckmb (on-die network) that may reset this bit when sending an interrupt to the target core.
Thanks for reply,
When cores are running at 533MHz, total power consumption is 32W
When we decrease frequency to 100MHz, power reduces to 26W
So, this clock freqeuncy is effective in power consumption.
Now, I applied the change that you suggested. It does not work!
using sccGui Send Flit Widget, I made the specified bit 0 for 10 cores
in order to make sure that the value is written there and it has not changed, i read back the registers, the stop clock bit is zero.
However, there is no chanage in total power consumption.
So, there should be another configuration there which also affects this behavior. The CPU clock does not turn off by just setting this bit to zero.
correct me, if I am wrong.
You mentioned in one of your posts that you wanted to turn off the memory controllers completely. Admittedly, I'm still confused about why you would want to do that ... not to say that you don't have a good reason.
Note, however, that the power value you see in the Performance Meter in the SCC GUI does not include a contribution from the memory controllers. That value is obtained by multiplying 3.304 * 9.505 = 31.405. Please don't make too much of this actual value. The chip was in an untrained state not running SCC Linux. The purpose is just to show that the power reading comes from the voltage and curent beside 3V3SCC.
The attached figure SCCPerfMeter shows the ouput of the sccBMC -c "status" command and the power reading from the SCC Performance Meter in the
SCCPerfMeter.png 259.9 K